Recently, synchronous memory for carrying out operations synchronized with a clock signal has been used as the main memory in personal computers and the like. With DDR (double data rate) synchronous memory, which is one type of synchronous memory, input/output data must be accurately synchronized with an external clock. Therefore, it is necessary to generate an internal clock synchronized with the external clock by using a DLL circuit.
FIG. 6 is a circuit diagram of an ordinary DLL circuit.
As shown in FIG. 6, the ordinary DLL circuit includes a delay line 20 having a plurality of cascade-connected delay elements 10. The external clock signal CLK is supplied to the first stage delay element 10a. The output-producing delay element 10 is selected from the plurality of delay elements 10 by a selector 30. Therefore, the amount by which the internal clock signal LCLK is delayed with respect to the external clock signal CLK increases as the stage of the selected delay element increases.
The selection operation carried out by the selector 30 is controlled by a phase comparator 40. The phase comparator 40 is a circuit for comparing the phase of the external clock signal CLK and the phase of the internal clock signal LCLK, which passes through a replica buffer 50. In the phase comparator 40, when the phase of the internal clock signal LCLK is delayed with respect to that of the external clock signal CLK, the phase of the internal clock signal LCLK should be advanced, and a lower stage delay element 10 will be selected by the selector 30. On the other hand, when the phase of the internal clock signal LCLK is advanced with respect to that of the external clock signal CLK, the phase of the internal clock signal LCLK should be delayed, and a higher stage delay element 10 will be selected by the selector 30.
However, the frequency of the external clock signal CLK varies according to the specifications of the end product and the operation mode. Therefore, a demand has arisen for a DLL circuit that is compatible with certain frequency bands. However, in order for compatibility to be provided over a wide clock frequency range, the number of stages of the delay elements 10 constituting the delay line 20 must be increased, and the delay produced by a single delay element 10 must be set to a low value. Therefore, when an attempt is made to increase the compatible frequency range, a problem arises in that the area used by the DLL circuit on the chip increases.
On the other hand, since the frequencies of the clock signals are extremely high, a demand has arisen in recent years for an increase in the quality of the clock signal transmitted by the delay line. Using differential circuits as the delay elements 10 constituting the delay line 20 is an effective way to enhance the quality of the clock signal transmitted by the delay line (see John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE JSSC, Vol. 31 No. 11, November 1996).
A dual-loop DLL circuit having a feedback loop using a positive signal and feedback loop using an inverted clock signal has been proposed as a method for increasing signal quality (see Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, Joo Hwan Cho, Pil Soo Lee, Jin Hong Ahn, and Jin Yong Chung, “A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM”, IEEE JSSC, Vol. 37 No. 6, June 2002).
However when differential circuits are used as the delay elements 10, the scale of the circuit will be further increased. Therefore, when an attempt is made to widen the compatible frequency range and increase the quality of the clock signal transmitted by the delay line, problems have occurred in that the area used on the chip is considerably increased.